The present invention relates to the field of semiconductor device manufacturing and more particularly methods for forming semiconductor devices having asymmetrical dopant profiles.
Semiconductor devices such as asymmetric metal oxide semiconductor field effect transistors (MOSFETs) are known in the art to provide performance advantages over their symmetrical double-halo and conventional MOSFET counterparts. Advantages of asymmetric MOSFETS include an ability to produce higher drive current (Idsat) and higher transconductance (gm), both of which are desirable MOSFET properties. The higher drive current and transconductance increases the semiconductor device""s speed, which correspondingly improves overall device performance.
Conventional methods for forming asymmetric MOSFETs currently include using a combination of critical patterning and implanting processes or using implant techniques that require the use of restrictive layout designs to form asymmetrically doped source or drain regions in the semiconductor device. For example, in one prior art method, the semiconductor device substrate is patterned to selectively expose and implant dopant species into only the source region, thereby forming the asymmetrically doped regions in the semiconductor device. Limitations of this prior art method include the photolithography tool""s alignment and patterning capabilities. Patterning and implanting only the source region (and not the drain region) of the semiconductor device requires that the photolithography tool be capable of precisely patterning resist feature openings on only one side of the gate electrode. Because the source and drain regions are separated by a dimension that is effectively only as wide as the gate electrode, any misalignment of the resist feature opening relative to the gate electrode can result in insufficiently implanting the source side or undesirably implanting the drain side of the semiconductor device. This issue becomes even more problematic as the gate electrode""s critical dimensions decrease.
In another prior art method, the semiconductor device substrate is tilted and then implanted from directions such that only one side (source side or drain side) of the semiconductor device to receive dopant species. This prior art method is undesirable because the asymmetrically doped regions for all of the semiconductor devices on the substrate must be arranged, during design layout, such that they are all oriented in the same direction. This restricts the layout possibilities that can be used to form the integrated circuit (IC). Furthermore, because the asymmetric implant may be performed while tilting the semiconductor device substrate, the semiconductor device packing density must also be considered when arranging the layout. Additionally, shadowing effects produced by resist features can partially or completely block an implant intended for a region of the semiconductor device substrate.